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Philips Semiconductors Product specification TrenchMOS transistor Standard level FET GENERAL DESCRIPTION N-channel enhancement mode standard level field-effect power transistor in a plastic envelope suitable for surface mounting. Using 'trench' technology the device features very low on-state resistance. It is intended for use in automotive and general purpose switching applications. BUK7640-100A QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 10 V MAX. 100 37 138 175 40 UNIT V A W C m PINNING - SOT404 PIN 1 2 3 mb gate drain (no connection possible) source drain DESCRIPTION PIN CONFIGURATION mb SYMBOL d g 2 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 k Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 100 100 20 37 26 149 138 175 UNIT V V V A A A W C THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS Minimum footprint, FR4 board TYP. 50 MAX. 1.1 UNIT K/W K/W December 1999 1 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET STATIC CHARACTERISTICS Tj= 25C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VDS = 100 V; VGS = 0 V; VGS = 20 V; VDS = 0 V VGS = 10 V; ID = 25 A Tj = 175C Tj = 175C MIN. 100 89 2 1 - BUK7640-100A TYP. 3 0.05 2 30 - MAX. 4 4.4 10 500 100 40 108 UNIT V V V V V A A nA m m DYNAMIC CHARACTERISTICS Tmb = 25C unless otherwise specified SYMBOL Ciss Coss Crss td on tr td off tf Ld Ls PARAMETER Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance CONDITIONS VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. TYP. 1720 216 133 12 55 48 30 2.5 7.5 MAX. 2293 259 182 18 83 67 42 UNIT pF pF pF ns ns ns ns nH nH VDD = 30 V; Rload =1.2; VGS = 10 V; RG = 10 Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 37 A; VGS = 0 V IF = 37 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 30 V TYP. 0.85 1.1 70 0.24 MAX. 37 149 1.2 UNIT A A V V ns C December 1999 2 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET AVALANCHE LIMITING VALUE SYMBOL W 1 DSS BUK7640-100A PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 26 A; VDD 25 V; VGS = 10 V; RGS = 50 ; Tmb = 25 C MIN. - TYP. - MAX. 31 UNIT mJ 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 1000 ID/A RDS(ON)=VDS/ID 100 tp = 1us 10us 100us 10 1ms DC 10ms 100ms 0 20 40 60 80 100 Tmb / C 120 140 160 180 1 1 10 VDS/V 100 1000 Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp 120 110 100 90 80 70 60 50 40 30 20 10 0 ID% Normalised Current Derating 10 Zth/(K/W) 1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0 0.001 1E-07 0 20 40 60 80 100 Tmb / C 120 140 160 180 1E-05 t/s 1E-03 1E-01 1E+01 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); VGS 10 V Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 1 For maximum permissible repetive avalanche current see fig.18. December 1999 3 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET BUK7640-100A 50 45 40 35 30 25 20 15 10 5 0 0 Drain Current, ID (A) Tj = 25 C VGS = 10V 8V 6V 40 35 30 25 5.4 V 5.2 V 5V 4.8 V 4.6 V 4.4 V 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 20 15 10 5 0 Drain current, ID (A) VDS > ID X RDS(ON) Tj = 25 C 175 C 0 1 2 3 4 5 6 7 8 9 10 Gate-source voltage, VGS (V) Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS) Fig.8. Typical transfer characteristics. ID = f(VGS) 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 Drain-Source On Resistance, RDS(on) (Ohms) 5V 4.8 V 5.2 V 5.4 V Tj = 25 C 70 gfs/S 60 50 40 6V 8V VGS = 10V 30 20 10 0 0 5 10 15 20 25 30 Drain Current, ID (A) 35 40 45 50 0 10 ID/A 20 30 40 Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID) Fig.9. Typical transconductance, Tj = 25 C. gfs = f(ID) Rds(on) normalised to 25degC 38 3 a RDS(ON) Ohm 36 34 2.5 2 32 30 28 26 1 2 3 VGS/V 4 5 0.5 -100 -50 0 50 100 Tmb / degC 150 200 1.5 1 Fig.7. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(VGS); conditions: ID = 25 A; Fig.10. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj) December 1999 4 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET BUK7640-100A 5 VGS(TO) / V max. BUK759-60 10 VGS / V 9 8 7 VDS = 14V VDS = 44V 4 typ. 3 min. 2 6 5 4 3 1 2 1 0 -100 0 -50 0 50 Tj / C 100 150 200 0 10 20 QG / nC 30 40 Fig.11. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.14. Typical turn-on gate-charge characteristics. VGS = f(QG) 1E-01 Sub-Threshold Conduction Source-Drain Diode Current, IF (A) 50 45 40 35 VGS = 0 V 1E-02 2% typ 98% 1E-03 30 25 20 15 10 175 C Tj = 25 C 1E-04 1E-05 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1E-06 0 1 2 3 4 5 Source-Drain Voltage, VSDS (V) Fig.12. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS Fig.15. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj WDSS% 120 3.5 3.0 110 100 90 80 70 60 Capacitance / pF 2.5 2.0 1.5 1.0 0.5 0.0 0.01 Coss Crss 0.1 1 VDS/V 10 100 Ciss 50 40 30 20 10 0 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.13. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz Fig.16. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A December 1999 5 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET BUK7640-100A + L VDS VGS 0 RGS T.U.T. R 01 shunt VDD + RD VDS VDD -ID/100 VGS 0 RG T.U.T. - Fig.17. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD ) Fig.19. Switching test circuit. 100 IAV 25C 10 Tj prior to avalanche 150C 1 0.001 0.01 0.1 1 10 Avalanche Time, tAV (ms) Fig.18. Maximum permissible repetitive avalanche current(IAV) versus avalanche time(tAV) for unclamped inductive loads. December 1999 6 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) BUK7640-100A SOT404 A E A1 mounting base D1 D HD 2 Lp 1 3 b c Q e e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.40 14.80 Q 2.60 2.20 OUTLINE VERSION SOT404 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-12-14 99-06-25 Fig.20. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". December 1999 7 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Standard level FET MOUNTING INSTRUCTIONS Dimensions in mm 11.5 BUK7640-100A 9.0 17.5 2.0 3.8 5.08 Fig.21. SOT404 : soldering pattern for surface mounting. DEFINITIONS Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. December 1999 8 Rev 1.000 |
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